Prove acceptance readiness before factory and site testing

How infrastructure managers, suppliers, and independent verifiers can combine formal verification, simulation, and automated hardware-in-the-loop testing to find defects before acceptance, not during it.

Defects and omissions from earlier phases surface throughout a signaling project. But acceptance testing is where they converge, and where the delays built up over time become undeniable. 

When issues first appear during factory acceptance testing (FAT) or site acceptance testing (SAT), corrections are at their most expensive, and schedules have the least slack. Manual testing scales poorly, and coverage is hard to demonstrate. Whether you are commissioning a COTS interlocking, verifying ERTMS trackside data, or qualifying a supplier design, confidence tends to arrive only at the end. 

Three complementary techniques can move that confidence earlier. Formal verification proves that selected safety properties hold in every reachable state, not only in the scenarios someone thought to test. Simulation exercises sequences, degraded modes, and corner cases before any hardware is involved. Automated hardware-in-the-loop (HIL) testing then runs against real or emulated control equipment ahead of FAT, catching integration issues while they are still cheap to fix. 

In this webinar, Benjamin Blanc and Gunnar Smith from Prover will explain how these techniques work together to produce an acceptance readiness package: evidence that a system is ready for FAT and SAT before those windows open.